1. Field of the Invention
The present invention relates to manufacturing of semiconductor devices. More specifically, the present invention relates to a method and system for correlating a physical model representation to a pattern layout.
2. Related Art
As integration densities on a semiconductor chip continue to increase at an exponential rate, it is becoming progressively more difficult to compensate for optical effects incurred during the optical lithography process. These optical effects can cause undesirable distortion, lower product yield, and reduce product profitability.
To remedy this problem, designers often use a model-based optical proximity correction (OPC) process to adjust the layout and compensate for optical effects. During OPC, edges in the layout are divided into segments, and each segment is adjusted with a positive or negative bias based upon a deviation between the desired layout and the simulated layout. In addition, one can use assist features (AFs), which are additional chrome regions outside the circuit areas, to assist formation of the desired feature shapes or to enhance the depth of focus for the layout.
To produce a high-quality layout on a wafer, process engineers generally perform iterative prediction-and-correction cycles with trial mask patterns. The quality of the final mask largely depends on the accuracy of the simulation model used in each cycle. However, the cost of accurate simulation becomes increasingly high as the competitive semiconductor market pushes the processing technologies to deep-sub-micron levels. Today's layout resolution has long surpassed the wavelength of visible light and requires short-wavelength light sources such as X-Ray sources. As a result, complex and costly electromagnetic modeling is necessary to accurately capture the optical imaging behavior of a modern lithography system.
Hence, what is needed is a method and system that facilitates expedited and accurate modeling of an optical imaging system.